The present invention relates to power device technology, and more particularly to improved edge termination for charge balance power devices.
The charge balance concept is a promising evolution in the power device technology. Some of the defining performance characteristics for the power switch are its on-resistance, breakdown voltage and switching speed. Depending on the requirements of a particular application, a different emphasis may be placed on each of these performance criteria. For example, in the mid to high voltage range (i.e., 60 to 2,000 volts), a conventional device suffers from high resistivity, since the drift region needs to be lightly doped in order for the device to sustain high voltages during the blocking state. The high resistivity of the drift region results in higher source-to-drain on-resistance RDSon, which in turn results in high power losses. Because of the inverse relationship between RDSon, and the breakdown voltage, improving the breakdown voltage performance of the device while maintaining a low RDSon poses a challenge.
Various charge balancing structures in the device drift region, including buried electrodes, opposite polarity pillars and floating regions, have been developed to address this challenge with varying degrees of success. The charge balancing techniques aim to maintain a substantially uniform electric field within the drift region in order to increase the breakdown voltage of the device. Thus, for the same breakdown voltage, the drift region can be higher doped thereby reducing RDSon.
However, one problem with the design of charge balance devices is the edge termination area. It is a challenge to achieve charge balance at the interface between the active region and the termination region since an opposing junction to couple to the last active cell can be difficult to implement. If all the active cells are identically charge balanced except at the active to termination interface region, then this interface region becomes the limiting factor in achieving high breakdown voltage. The edge termination breakdown at low current levels does not hinder device performance however, during high current avalanche events such as unclamped inductive load (UIL) switching, the limited area of the termination region relative to the active array cannot handle the power losses. This detrimentally impacts the safe operating area (SOA) of the device.
Thus, what is desirable is a structure and method that enable a high device blocking capability, low on-resistance, and high current handling capability, particularly the capability to sustain high avalanche current in the active to termination interface region.